Failure Analysis Services Tailored to your Needs
At Nanolab Technologies we recognize that Failure Analysis is a very important component in achieving successful results. Time, cost, and successful completion of analytical information will not be achieved without successful and cost-effective Failure Analysis.
The proper balance of education, training, experience, and skills of the people who do the work is important when choosing which lab to use. At Nanolab Technologies, we take great pride in our ability to offer the best people with the highest levels of experience and skills, the finest technologies, and the correct knowledge based analysis techniques to solve our customers’ problems.
Failure Analysis Information Includes:
- Failures in First Silicon: rapid response is essential to developing a working product
- Production Failures: quickly overcome obstacles to improved yields and increase profitability
- Reliability Test Failures: defects are analyzed to determine if they are one-off’s or latent issues
- Field Failures: determine if defects are latent process or device errors, caused by operator error, one-time over-voltage events, or customer design problems
Nanolab Technologies’ Discovery process gathers essential information from the customer before we begin. This procedure is important because most failure samples offer only one chance at isolating, localizing, and characterizing a defect. Once destructive techniques are used, the original state of the sample is lost forever.
With years of successful experience in Failure Analysis, we recommend you consult with one of our Failure Analysis analysts to review the best knowledge based flow and techniques to achieve the optimum results that help solve your problems.
(Level I, Level II, & Level III)
Level 1 (opens and shorts):
- Optical inspection and images of the top and bottom of the device, Curve trace to confirm failure, X-ray imaging to check for wire integrity or solder bump in Flip Chips, C-SAM to check for delamination (popcorn).
Level 2 (opens, short, leakage):
- All of Level 1 plus:
- Die side: decap/sample prep, optical inspection of die.
- Package side: FMI or parallel-lapping, checking fault status at each layer.
Level 3 (leakage):
- All of Levels 1 and 2 plus:
- If a site is found then parallel-lapping with step-by-step optical and/or SEM inspection. If needed FIB-SEM.
Level 1: Non-Destructive
Non-destructive techniques may isolate and localize the defect and are always applied first. They can include:
- Electrical failure verification of all components, including unpowered and powered Curve Tracing and Latch Up testing
- External visual optical inspection
- X-ray for internal anomalies
- CSAM to check for delamination, cracks, flip chip bump integrity, bonded wafers, and packaging issues
- TDR for changes in impedance
- FMI analyses to identify hot spots
Level 2: Destructive
When nondestructive testing does not isolate or localize a defect, we turn to a discrete destructive technique to enable internal inspection of the device. We access standard semiconductor components as well as ceramic chip capacitors, PCB’s, Tantalum caps, and Foil caps.
We often uncover the anomalous condition at this point and don’t need to do further analysis. Typical tools employed for this Level include:
- Laser-based localization
Level 3: Full
If Levels 1 Level 2 don’t yield sufficient data, a careful series of steps ensue to take us deeper into the component’s circuitry and molecular composition. The exact sequence is determined with information obtained in Discovery and Levels 1 and 2.
Highly skilled technicians use polishing wheels to make serial slices that permit our scientists to analyze inner structures using the appropriate tools. These can include:
- Optical microscopy